There are various methods of testing whether an integrated circuit device is normal or defective, including methods of testing one integrated circuit device, and methods of testing a plurality of integrated circuit devices at the same time to reduce test cost. FIG. 1 is a diagram of a test system for testing a plurality of integrated circuit devices at the same time. The known test system 100 has a controller 110 that generates test signals TESTS for testing integrated circuit devices that can be connected to test board units 120, 130, 140 and 150. The test signals TESTS are passed first through m-th relays, RL1 through RLm, that selectively pass or cut-off the test signals TESTS in response to relay control signals RLCT1 through RLCTm generated in the controller 110. The test board units 120, 130, 140 and 150 test integrated circuit devices connected thereto and generate first through m-th test result signals TSTRS1 through TSTRSm. a storage unit 160 temporarily stores the first through m-th test result signals, TSTRS1 through TSTRSm, and provides the signals to the controller 110.
Test signals TESTS are generated according to a test condition set by a test program of the controller 110. The test of integrated circuit devices may be performed on only one item, or continuously on tens or hundreds of test items. The controller 110 has a distributor (not shown) and a plurality of drivers (not shown) for providing the test signals TESTS to a plurality of integrated circuit devices. The test signals TESTS are provided to the first through m-th test board units 120, 130, 140 and 150 through the first through m-th relays RL1 through RLm. In the initial stage for testing, contacts of the first through m-th relays RL1 through RLm are connected to each other. The first through m-th test board units 120, 130, 140 and 150 include first through m-th device under test (DUT) boards DUT1 through DUTm, respectively, and first through m-th comparison units 125, 135, 145, and 155, respectively.
Integrated circuit devices may be connected to the first through m-th DUT boards DUT1 through DUTm. The first through m-th DUT boards DUT1 through DUTm receive the test signals TESTS, test the integrated circuit devices, and then generate first through m-th DUT signals DUTS1 through DUTSm.
The integrated circuit devices each have a plurality of pins to be tested, n, so that each of the DUT signals, DUTS1 through DUTSm, is an n-bit signal with each bit testing one of the plurality of pins. The first through m-th DUT signals, DUTS1 through DUTSm, are provided to the first through m-th comparison units 125, 135, 145, and 155, respectively, so as to determine whether or not the signals provided by the plurality of pins of the integrated circuit device are valid or defective (invalid). Data that is expected for valid signals from each of the pins, normal data, is stored in the first through m-th comparison units 125, 135, 145, and 155. The first through m-th DUT signals DUTS1 through DUTSm are then compared with the normal data. The first through m-th DUT signals DUTS1 through DUTSm that are compared with the normal data and the results of the comparison are provided as first through m-th test result signals TSTRS1 through TSTRSm to the storage unit 160.
The first through m-th test result signals TSTRS1 through TSTRSm stored in the storage unit 160 are sequentially provided as stored test result signals CTSTRS to the controller 110. The controller 110 analyzes the stored test result signals CTSTRS and generates first through m-th relay control signals RLCT1 through RLCTm that control the first through m-th relays RL1 through RLm. After the stored test result signal CTSTRS is analyzed, and if, for example, the integrated circuit devices connected to the first through third DUT boards DUT1 through DUT3 are determined to be defective, the controller 110 disconnects the first through third relays RL1 through RL3, and maintains the connections of the remaining relays RL4 through RLm.
In order to maintain the disconnected states of the first through third relays RL1 through RL3 even when the controller 110 initializes the test system 100 to test a next test item, the controller 110 should store and process a variety of data.
However, in the prior art test system 100, when a plurality of integrated circuit devices are tested for a plurality of test items, test results are read for each integrated circuit device every time, and the controller 110 determines whether or not an integrated circuit device is normal. Accordingly, the test process may take a considerable amount of time. For example, when 100 integrated circuit devices, each having 8 pins, are tested for 100 test items in the prior art test system 100, the amount of data to be processed by the controller 110 is calculated as the number of integrated circuit devices×the number of pins of an integrated circuit device×the number of test items=100×8×100=80,000. Thus, in order to complete tests for 100 integrated circuit devices at the same time, 80,000 data items must be read and processed, such that test time increases greatly. Also, a lot of data communications between the test system and the controller may be necessary, which may significantly increase the test time.